• DigRF v4 Decodes 
  • Low-speed (26 Mb/s) 
  • Medium-speed (1248 Mb/s) 
  • High-speed (1456 Mb/s) 
• DigRF v3 Decodes 
  • Low-speed (6.5 Mb/s) 
  • Medium-speed (26 Mb/s) 
  • High-speed (312 Mb/s) 
• Convert DigRF 3G and v4 I and Q digital data to corresponding analog waveforms 
• Correlate analog waveforms with protocol decode on one screen 
• View decoded data in hexadecimal format 
• Decode information expands as the time base is adjusted or zoomed 
• Convenient table display with quick “Zoom to byte” capability 
• Quick search capability for specific message packets

The APEX Turbine Data System (DS) is the next generation of data acquisition, control, setup, and online analysis. It reliably acquires time-synchronized data from a network of digitizers, regardless of sample rate or sensor type.

• Intuitive, icon-based setup and control
•  Spreadsheet-style channel configuration 
• Snapshot display with data export 
• Independent sampling rates for each instrument 
• Real-time online graphical data analysis 
• Client / server architecture with multiple displays 
• Synchronization of different data sources 
• Detect/process events for close-loop control 
• Post-acquisition analysis methods and data playback 
• Easily create Virtual/Calculated channels based on physical channel data

• Autonomous Modal Parameter Estimation Procedure 
• Multiple Live Parameter Estimation Windows 
• Task Oriented, Easy-To-Use Interface 
• Logical Operation Always "One-Click" away 
• Simplified "Copy & Paste" Data Management 
• Simplified Units Unification Tool 
• Based on MATLAB® Computational Engine Environment 
• Universal File Format (UFF) Data Access 
• Individual Data Channel Calibration

• Only BSDL files required to get the board up and running 
• Set up pin states – e.g. low, high, toggling 
• Trace shorts, opens and other signals 
• Easy low-level access to device pins/busses 
• Clear display of the pins/balls with variable zoom levels and split screen 
• View JTAG chain data as waveforms 
• Quickly find and monitor changing pins 
• Program devices with SVF and STAPL files 
• Real-time interaction 
• XJIntegration (use XJAnalyser functionality from other software)

• Reduce your time spent debugging boards due to high precision fault isolation 
• Improve your time to market and reduce project risk by early design verification 
• Reduce your test development time by reusing tests from prototype/design in manufacturing and field support 
• Ongoing time savings by test reuse across projects

• Reduce flash programming times 
• SPI, QSPI, parallel NOR flash devices supported 
• Support for NAND flash devices available on request 
• Shortened development cycles 
• No need for additional equipment 
• Can be used for fast firmware upgrade 
• No FPGA development required